Nordic Semiconductor /nrf5340_application /PDM0_NS /MCLKCONFIG

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Interpret as MCLKCONFIG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PCLK32M)SRC

SRC=PCLK32M

Description

Master clock generator configuration

Fields

SRC

Master clock source selection

0 (PCLK32M): 32 MHz peripheral clock

1 (ACLK): Audio PLL clock

Links

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